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d a t a sh eet product speci?cation file under integrated circuits, ic06 september 1993 integrated circuits 74hc/hct5555 programmable delay timer with oscillator for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
september 1993 2 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 features positive and negative edge triggered retriggerable or non-retriggerable programmable delay minimum: 100 ns maximum: depends on input frequency and division ratio divide-by range of 2 to 2 24 direct reset terminates output pulse very low power consumption in triggered start mode 3 oscillator operating modes: C rc oscillator C crystal oscillator C external oscillator device is unaffected by variations in temperature and v cc when using an external oscillator automatic power-on reset schmitt trigger action on both trigger inputs direct drive for a power transistor low power consumption in active mode with respect to ttl type timers high precision due to digital timing output capability: 20 ma i cc category: msi. applications motor control attic fan timers delay circuits automotive applications precision timing domestic appliances. general description the 74hc/hct5555 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct5555 are precision programmable delay timers which consist of: 24-stage binary counter integrated oscillator (using external timing components) retriggerable/non-retriggerable monostable automatic power-on reset output control logic oscillator control logic overriding asynchronous master reset (mr). quick reference data gnd = 0 v; t amb = 25 c; t r = t f = 6 ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d = c pd x v cc 2 x f i + s (c l x v cc 2 x f o ) where: f i = input frequency in mhz f o = output frequency in mhz s (c l x v cc 2 x f o ) = sum of outputs. c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v. ordering information symbol parameter conditions typ. unit t phl /t plh propagation delay c l = 15 pf; v cc = 5 v a, b to q/ q2424ns mr to q/ q1920ns rs to q/ q2628ns c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per buffer notes 1 and 2 23 36 pf extended type number package pins pin position material code 74hc/hct5555n 16 dil plastic sot38z 74hc/hct5555d 16 so16 plastic sot109a
september 1993 3 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 pinning symbol pin description rs 1 clock input/oscillator pin r tc 2 external resistor connection c tc 3 external capacitor connection a 4 trigger input (positive-edge triggered) b 5 trigger input (negative-edge triggered) rtr/ r tr 6 retriggerable/non-retriggerable input (active high/active low) q 7 pulse output (active low) gnd 8 ground (0 v) q 9 pulse output (active high) s 0 - s 3 10, 11, 12, 13 programmable input osc con 14 oscillator control mr 15 master reset input (active high) v cc 16 positive supply voltage fig.1 pin configuration. handbook, halfpage 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 5555 gnd v cc mga642 r tc c tc q rs osc con mr a b rtr/ rtr q 0 s 1 s 2 s s 3 fig.2 iec logic diagram. handbook, halfpage mga643 1 i = 0 s r r & ct = 0 ct = m r v16 7 9 17 16g17 cx rx 1 2 4 8 x / y ctrdivm [t] y = 0 y = 15 ! g + 0 15 10 11 12 13 2 3 14 1 6 4 5 15
september 1993 4 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 fig.3 functional diagram. handbook, full pagewidth mga644 r tc c tc monostable circuitry q rs osc con mr a b 1 14 15 4 5 6 9 7 2 3 10 11 12 13 power-on reset rtr/rtr output stage q 24 - stage counter cp cd 012 ssss 3 functional description the oscillator configuration allows the design of rc or crystal oscillator circuits. the device can operate from an external clock signal applied to the rs input (r tc and c tc must not be connected). the oscillator frequency is determined by the external timing components (r t and c t ), within the frequency range 1 hz to 4 mhz (32 khz to 20 mhz with crystal oscillator). in the hct version the mr input is ttl compatible but the rs input has cmos input switching levels. the rs input can be driven by ttl input levels if rs is tied to v cc via a pull-up resistor. the counter divides the frequency to obtain a long pulse duration. the 24-stage is digitally programmed via the select inputs (s 0 to s 3 ). pin s 3 can also be used to select the test mode, which is a convenient way of functionally testing the counter. the 5555 is triggered on either the positive-edge, negative-edge or both. trigger pulse applied to input a for positive-edge triggering trigger pulse applied input b for negative-edge triggering trigger pulse applied to inputs a and b (tied together) for both positive-edge and negative triggering. the schmitt trigger action in the trigger inputs, transforms slowly changing input signals into sharply defined jitter-free output signals and provides the circuit with excellent noise immunity. the osc con input is used to select the oscillator mode, either continuously running (osc con = high) or triggered start mode (osc con = low). the continuously running mode is selected where a start-up delay is an undesirable feature and the triggered start mode is selected where very low power consumption is the primary concern. the start of the programmed time delay occurs when output q goes high (in the triggered start mode, the previously disabled oscillator will start-up). after the programmed time delay, the flip-flop stages are reset and the output returns to its original state. an internal power-on reset is used to reset all flip-flop stages. the output pulse can be terminated by the asynchronous overriding master reset (mr), this results in all flip-flop stages being reset. the output signal is capable of driving a power transistor. the output time delay is calculated using the following formula (minimum time delay is 100 ns): once triggered, the output width may be extended by retriggering the gated, active high-going input a or the active low-going input b. by repeating this process, the output pulse period (q = high, q = low) can be made as long as desired. this mode is selected by rtr/ rtr = high. a low on rtr/ rtr makes, once triggered, the outputs (q, q) independent of further transitions of inputs a and b. 1 f i -- - division ratio (s).
september 1993 5 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 n dbook, full pagewidth mga655 r tc c tc q rs osc con mr a b rtr/ rtr q 0 s 1 s 2 s s 3 cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q cp cd q v cc fig.4 logic diagram.
september 1993 6 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 test mode set s 3 to a logic low level, this will divide the 24 stage counter into three, parallel clocking, 8-stage counters. set s 0 , s 1 and s 2 to a logic high level, this programs the counter to divide-by 2 8 (256). apply a trigger pulse and clock in 255 pulses, this sets all flip-flop stages to a logic high level. set s 3 to a logic high level, this causes the counter to divide-by 2 24 . clock one more pulse into the rs input, this causes a logic 0 to ripple through the counter and output q/ q goes from high-to-low level. this method of testing the delay counter is faster than clocking in 2 24 (16 777 216) clock pulses. function table notes 1. h = high voltage level l = low voltage level x = don't care - = low-to-high transition = high-to-low transition. inputs outputs mr a bq q hxxlh l - x one high level output pulse one low level output pulse lx one high level output pulse one low level output pulse
september 1993 7 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 delay time selection select inputs output q/ q (frequency dividing) s 3 s 2 s 1 s 0 binary decimal llll2 1 2 lllh2 2 4 llhl2 3 8 llhh2 4 16 lhll2 5 32 lhlh2 6 64 lhhl2 7 128 lhhh2 8 256 ..... . hlll2 17 131 072 hllh2 18 262 144 hlhl2 19 524 288 hlhh2 20 1 048 576 hhl l2 21 2 097 152 hhlh2 22 4 194 304 hhhl2 23 8 388 608 hhhh2 24 16 777 216 fig.5 timing diagram. timing example shown for s 3 , s 2 , s 1 , s 0 = 0011 (binary 2 4 , decimal 16). handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 rs mr a q mga649
september 1993 8 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: parallel outputs, bus driver; serial output, standard i cc category: msi. dc characteristics for 74hc sym- bol parameter t amb ( c) unit test condition + 25 - 40 to + 85 - 40 to + 125 v cc (v) v i other min typ max min max min max v oh high level output voltage q and q outputs 1.9 4.4 5.9 2 4.5 6.0 - - - 1.9 4.4 5.9 - - - 1.9 4.4 5.9 - - - v v v 2.0 4.5 6.0 i o = - 20 m a v oh high level output voltage q and q outputs 3.98 5.48 4.32 5.81 - - 3.84 5.34 - - 3.7 5.2 - - v v 4.5 6.0 i o = - 6.0 ma i o = - 7.8 ma v oh high level output voltage q and q outputs 3.3 4.8 - - - - 3 4.5 - - 2.7 4.2 - - v v 4.5 6.0 i o = - 20 ma i o = - 20 ma v ol low level output voltage q and q outputs - - - 0 0 0 0.1 0.1 0.1 - - - 0.1 0.1 0.1 - - - 0.1 0.1 0.1 v v v 2.0 4.5 6.0 i o = 20 m a v ol low level output voltage q and q outputs - - 0.15 0.15 0.26 0.26 - - 0.33 0.33 - - 0.40 0.40 v v 4.5 6.0 i o = 6.0 ma i o = 7.8 ma v ol low level output voltage q and q outputs - - - - 0.9 0.9 - - 1.14 1.14 - - 1.34 1.34 v v 4.5 6.0 i o = 20 ma i o = 25 ma v ih high level input voltage rs input 1.7 3.6 4.8 - - - - - - 1.7 3.6 4.8 - - - 1.7 3.6 4.8 - - - v v v 2 4.5 6.0 v il low level input voltage rs input - - - - - - 0.3 0.9 1.2 - - - 0.3 0.9 1.2 - - - 0.3 0.9 1.2 v v v 2.0 4.5 6.0
september 1993 9 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 v oh high level output voltage r tc output 3.98 5.48 - - - - 3.84 5.34 - - 3.7 5.2 - - v v 4.5 6.0 rs = gnd; osc con = v cc i o = - 2.6 ma i o = - 3.3 ma 3.98 5.48 - - - - 3.84 5.34 - - 3.7 5.2 - - v v 4.5 6.0 rs = v cc ; osc con = gnd; untriggered i o = - 0.65 ma i o = - 0.85 ma 1.9 4.4 5.9 2.0 4.5 6 - - - 1.9 4.4 5.9 - - - 1.9 4.4 5.9 - - - v v v 2.0 4.5 6.0 rs = v cc ; osc con = v cc i o = - 20 m a 1.9 4.4 5.9 2.0 4.5 6.0 - - - 1.9 4.4 5.9 - - - 1.9 4.4 5.9 - - - v v v 2 4.5 6.0 rs = v cc ; osc con = gnd; untriggered i o = - 20 m a v oh high level output voltage c tc output 3.98 5.48 - - - - 3.84 5.34 - - 3.7 5.2 - - v v 4.5 6.0 rs = v ih ; osc con = v ih i o = - 3.2 ma i o = - 4.2 ma v ol low level output voltage r tc output - - - - 0.26 0.26 - - 0.33 0.33 - - 0.4 0.4 v v 4.5 6 rs = v cc ; osc con = v cc i o = 2.6 ma i o = 3.3 ma - - - 0 0 0 0.1 0.1 0.1 - - - 0.1 0.1 0.1 - - - 0.1 0.1 0.1 v v v 2.0 4.5 6 rs = v cc ; osc con = v cc i o = 20 m a v ol low level output voltage c tc output - - - - 0.26 0.26 - - 0.33 0.33 - - 0.4 0.4 v v 4.5 6.0 rs = v il ; osc con = v il ; untriggered i o = 3.2 ma i o = 4.2 ma sym- bol parameter t amb ( c) unit test condition + 25 - 40 to + 85 - 40 to + 125 v cc (v) v i other min typ max min max min max
september 1993 10 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 ac characteristics for 74hc gnd = 0 v; t r = t f = 6 ns; c l = 50 pf. symbol parameter t amb ( c) unit test condition + 25 - 40 to + 85 - 40 to + 125 v cc (v) waveforms min typ max min max min max t plh /t phl propagation delay a, b to q, q - - - 77 28 22 240 48 41 - - - 300 60 51 - - - 360 72 61 ns ns ns 2.0 4.5 6.0 fig.6 t plh /t phl propagation delay mr to q, q - - - 61 22 18 185 37 31 - - - 230 46 39 - - - 280 56 48 ns ns ns 2.0 4.5 6.0 fig.7 t plh /t phl propagation delay rs to q, q - - - 83 30 24 250 50 43 - - - 315 63 54 - - - 375 75 64 ns ns ns 2.0 4.5 6.0 fig.8; note 1 t thl /t tlh output transition time - - - 19 7 6 75 15 13 - - - 95 19 16 - - - 110 22 19 ns ns ns 2.0 4.5 6.0 fig.6 t w trigger pulse width a = high b = low 70 14 12 17 6 5 - - - 90 18 15 - - - 105 21 18 - - - ns ns ns 2.0 4.5 6.0 fig.6 t w master reset pulse width high 70 14 12 19 7 6 - - - 90 18 15 - 105 21 18 - - - ns ns ns 2.0 4.5 6.0 fig.7 t w clock pulse width rs; high or low 80 16 14 25 9 7 - - - 100 20 17 - - - 120 24 20 - - - ns ns ns 2.0 4.5 6.0 fig.8 t w minimum output pulse width q = high, q = low - - - 275 100 80 - - - - - - - - - - - - - - - ns ns ns 2.0 4.5 6.0 fig.6; note 1 t rt retrigger time a, b - - - 0 0 0 - - - - - - - - - - - - - - - ns ns ns 2.0 4.5 6.0 fig.10; note 2 r ext external timing resistor 5 1 - - 1000 1000 - - - - - - - - - - k w k w 2.0 5.0 fig.13 c ext external timing capacitor 50 50 no limits pf pf 2.0 5.0 fig.13 t rem removal time mr to a, b 120 24 20 39 14 11 - - - 150 30 26 - - - 180 36 31 - - - ns ns ns 2.0 4.5 6.0 fig.7
september 1993 11 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 notes 1. one stage selected. 2. it is possible to retrigger directly after the trigger pulse, however the pulse will only be extended, if the time period exceeds the clock input cycle time divided by 2. 3. one stage selected. the termination of the output pulse remains synchronized with respect to the falling edge of the rs clock input. 4. one stage selected. the termination of the output pulse is no longer synchronized with respect to the falling edge of the rs clock input. f max maximum clock pulse frequency 2 10 12 5.9 18 21 - - - 1.8 8 10 - - - 1.3 6.6 8 - - - mhz mhz mhz 2.0 4.5 6.0 fig.8; note 3 f max maximum clock pulse frequency 6 30 35 24.8 75 89 - - - 4.8 24 28 - - - 4 20 24 - - - mhz mhz mhz 2.0 4.5 6.0 fig.9; note 4 symbol parameter t amb ( c) unit test condition + 25 - 40 to + 85 - 40 to + 125 v cc (v) waveforms min typ max min max min max
september 1993 12 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family speci?cations . output capability: non-standard; bus driver with extended speci?cation on v oh and v ol i cc category: msi. symbol parameter t amb ( c) unit test condition + 25 - 40 to + 85 - 0to + 125 v cc (v) v i other min typ max min max min max v oh high level output voltage q and q outputs 4.4 4.5 - 4.4 - 4.4 - v 4.5 i o = - 20 m a v oh high level output voltage q and q outputs 3.98 4.32 - 3.84 - 3.7 - v 4.5 i o = - 6 ma v oh high level output voltage q and q outputs 3.3 -- 3 - 2.7 - v 4.5 i o = - 20 ma v ol low level output voltage q and q outputs - 0 0.1 - 0.1 - 0.1 v 4.5 i o = 20 m a v ol low level output voltage q and q outputs - 0.15 0.26 - 0.33 - 0.40 v 4.5 i o = 6 ma v ol low level output voltage q and q outputs -- 0.9 - 1.14 - 1.34 v 4.5 - i o = 20 ma
september 1993 13 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 notes 1. the rs input has cmos input switching levels. 2. the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the following table. unit load coefficient v oh high level output voltage r tc output 3.98 -- 3.84 - 3.7 - v 4.5 rs = gnd; osc con =v cc i o = - 2.6 ma 3.98 -- 3.84 - 3.7 - v 4.5 rs = v cc ; osc con = gnd; untriggered i o = - 0.65 ma 4.4 4.5 - 4.4 - 4.4 - v 4.5 rs = v cc ; osc con = v cc i o = - 20 m a 4.4 4.5 - 4.4 - 4.4 - v 4.5 rs = v cc ; osc con = gnd; untriggered i o = - 20 m a v oh high level output voltage c tc output 3.98 -- 3.84 - 3.7 - v 4.5 rs = v ih ; osc con = v ih i o = - 3.2 ma v ol low level output voltage r tc output -- 0.26 - 0.33 - 0.4 v 4.5 rs = v cc ; osc con = v cc i o = 2.6 ma - 0 0.1 - 0.1 - 0.1 v 4.5 rs = v cc ; osc con = v cc i o = 20 m a v ol low level output voltage c tc output -- 0.26 - 0.33 - 0.4 v 4.5 rs = v il ; osc con = v il ; untriggered i o = 3.2 ma input unit load coefficient mr 0.35 a 0.69 b 0.50 rtr/ r tr 0.35 osc con 1.20 s 0 - s 2 0.65 s 3 0.40 symbol parameter t amb ( c) unit test condition + 25 - 40 to + 85 - 0to + 125 v cc (v) v i other min typ max min max min max
september 1993 14 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 ac characteristics for 74hct gnd = 0 v; t r = t f = 6 ns; c l = 50 pf. symbol parameter t amb ( c) unit test condition + 25 - 40 to + 85 - 40 to + 125 v cc (v) waveforms min typ max min max min max t plh /t phl propagation delay a, b to q, q - 28 48 - 60 - 72 ns 4.5 fig.6 t phl /t plh propagation delay mr to q, q - 24 41 - 51 - 62 ns 4.5 fig.7 t phl /t plh propagation delay rs to q, q - 32 54 - 68 - 81 ns 4.5 fig.8; note 1 t thl /t tlh output transition time - 715 - 19 - 22 ns 4.5 fig.6 t w trigger pulse width a = high b = low 21 12 - 26 - 32 - ns 4.5 fig.6 t w master reset pulse width high 14 5 - 18 - 21 - ns 4.5 fig.7 t w clock pulse width rs; high or low 16 9 - 20 - 24 - ns 4.5 fig.8 t w minimum output pulse width q = high, q = low - 100 ----- ns 4.5 fig.6 t rt retrigger time a, b - 0 ----- ns 4.5 fig.10; note 2 r ext external timing resistor 1 - 1000 ---- k w 4.5 fig.13 c ext external timing capacitor 50 no limits pf 4.5 fig.13 t rem removal time mr to a, b 24 14 - 30 - 36 - ns 4.5 fig.7 f max maximum clock pulse frequency 10 18 - 8 - 6.6 - mhz 4.5 fig.8; note 3 f max maximum clock pulse frequency 30 75 - 24 - 20 - mhz 4.5 fig.9; note 4
september 1993 15 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 notes 1. one stage selected. 2. it is possible to retrigger directly after the trigger pulse, however the pulse will only be extended, if the time period exceeds the clock input cycle time divided by 2. 3. one stage selected. the termination of the output pulse remains synchronized with respect to the falling edge of the rs clock input. 4. one stage selected. the termination of the output pulse is no longer synchronized with respect to the falling edge of the rs clock input.
september 1993 16 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 ac waveforms fig.6 waveforms showing the triggering of the delay timer by input a or b, the minimum pulse widths of the trigger inputs a and b, the output pulse width and output transition times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. handbook, full pagewidth t w q output mga653 q output 90% 10% a input b input v m (1) v m (1) t tlh t thl 90% 10% t w gnd v m (1) 90% 10% t w 90% 10% t phl t plh v m (1) t tlh t thl
september 1993 17 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 fig.7 waveforms showing the master reset (mr) pulse width, the master reset to outputs (q and q) propagation delays and the master reset to trigger inputs (a and b) removal time. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. handbook, full pagewidth t phl v m (1) t w t plh q output mr input mga652-1 v m (1) q output t rem a input b input v m (1) v m (1) v m (1) t rem
september 1993 18 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 fig.8 waveforms showing the clock (rs) to outputs (q and q) propagation delays, the clock pulse width and the maximum clock frequency. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. handbook, full pagewidth t phl v m (1) t w t plh q output rs input mga651 v cc 1 2 v m (1) q output 1/f max fig.9 waveforms showing the clock (rs) to outputs (q and q) propagation delays, the clock pulse width and the maximum clock frequency (output waveforms are not synchronized with respect to the rs waveform). (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. handbook, full pagewidth t phl v m (1) 1/f max t plh q output rs input mga654 v m (1) q output v m (1)
september 1993 19 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 fig.10 output pulse control using retrigger pulse (rtr/ rtr = high). (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. handbook, full pagewidth a input q output b input t w t rt t w t w t w t w mga650
september 1993 20 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 application information fig.11 test set-up for measuring forward transconductance g fs = di o /dv i at v o is constant (see fig.12) and mr = low. handbook, halfpage mga645 a output 100 f v cc input 0.47 f r = 560 k w bias i o (f = 1 khz) gnd v i m m fig.12 typical forward transconductance g fs as a function of the supply voltage at v cc at t amb = 25 c. handbook, halfpage mba333 14 12 10 8 6 4 2 0123456 g fs (ma/v) cc v (v) max. min. typ. fig.13 application information. c t curve at r t = 100 k w ; r2 = 200 k w . r t curve at c t = 1 nf; r2 = 2 x r t . rc oscillator frequency as a function of r t and c t at v cc = 2 to 6 v; t amb = 25 c. handbook, halfpage 10 3 mga647 10 4 10 5 10 6 10 10 5 10 3 10 4 10 2 f osc (hz) r ( ) t c ( f) t 10 ? 10 ? 10 ? 10 ? r t c t w m fig.14 example of an rc oscillator. typical formula for oscillator frequency: f osc 1 2.5 r t c t -------------------------------- = handbook, halfpage mga646 2 rs 1 mr (from logic) r tc c tc 3 r t c t c2 r2
september 1993 21 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 timing component limitations the oscillator frequency is mainly determined by r t c t , provided r2 ? 2r t and r2c2 << r t c t . the function of r2 is to minimize the influence of the forward voltage across the input protection diodes on the frequency. the stray capacitance c2 should be kept as small as possible. in consideration of accuracy, c t must be larger than the inherent stray capacitance. r t must be larger than the on resistance in series with it, which typically is 280 w at v cc = 2 v, 130 w at v cc = 4.5 v and 100 w at v cc = 6 v. the recommended values for these components to maintain agreement with the typical oscillation formula are: c t > 50 pf, up to any practical value, 10 k w< r t < 1 m w . in order to avoid start-up problems, r t >> 1 k w . typical crystal oscillator in fig.15, r2 is the power limiting resistor. for starting and maintaining oscillation a minimum transconductance is necessary, so r2 should not be too large. a practical value for r2 is 2.2 k w . above 14 mhz it is recommended replacement of r2 by a capacitor with a typical value of 35 pf. accuracy device accuracy is very precise for long time delays and has an accuracy of better than 1% for short time delays (1% applies to values 3 400 ns). tolerances are dependent on the external components used, either rc network or crystal oscillator. start-up using external clock the start of the timing pulse is initiated directly by the trigger pulse (asynchronously with respect to the oscillator clock). triggering on a clock high or clock low results in the following: clock = high; the timing pulse may be lengthened by a maximum of t w /2 (t w = clock pulse width) clock = low; the timing pulse may be shortened by a maximum of t w /2 (t w = clock pulse width). this effect can be minimized by selecting more delay stages. when using only one or two delay stages, it is recommended to use an external time base that is synchronized with the negative-edge of the clock. start-up using rc oscillator the first clock cycle is ? 35% of a time period too long. this effect can also be minimized by selecting more delay stages. start-up using crystal oscillator a crystal oscillator requires at least two clock cycles to start-up plus an unspecified period (ms) before the amplitude of the clock signal increases to its expected level. although this device also operates at lower clock amplitudes, it is recommended to select the continuously running mode (osc con = high) to prevent start-up delays. termination of the timing pulse the end of the timing pulse is synchronized with the falling edge of the oscillator clock. the timing pulse may lose synchronization under the following conditions: high clock frequency and large number of stages are selected. this depends on the dynamic relationship that exists between the clock frequency and the ripple through delay of the subsequent stages. synchronization when frequencies higher than those specified in the table 'synchronization limits' are used, the termination of timing pulse will lose synchronization with the falling edge of the oscillator. the unsynchronized timing pulse introduces errors, which can be minimized by increasing the number of stages used e.g. a 20 mhz clock frequency using all 24 stages will result in a frequency division of 16 777 225 instead of 16 777 216, an error of 0.0005%. the amount of error increases at high clock frequencies as the number of stages decrease. a clock frequency of 40 mhz and 4 stages selected results in a division of 18 instead of 16, a 12.5% error. application example: if a 400 ns timing pulse was required it would be more accurate to utilize a 5 mhz clock frequency using 1 stage or a 10 mhz clock frequency using 2 stages (due to synchronization with falling edge of the oscillator) than a 40 mhz clock frequency and 4 stages (synchronization is lost).
september 1993 22 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 minimum output pulse width the minimum output pulse width is determined by the minimum clock pulse width, plus the maximum propagation delay of a, b to q. the rising edge of q is dominated by the a, b to q propagation delay, while the falling edge of q is dominated by rs to q propagation delay. these propagation delays are not equal. the rs to q propagation delay is some what longer, resulting in inaccurate outputs for extremely short pulses. the propagation delays are listed in the section 'ac characteristics'. with these numbers it is possible to calculate the maximum deviation (an example is shown in fig.16). figure 16 is valid for an external clock where the trigger is synchronized to the falling edge of the clock only. the graph shows that the minimum programmed pulse width of 100 ns is: minimum of 4% too long typically 7% too long maximum of 10% too long. synchronization limits number of stages selected clock frequency (typical) 1 18 mhz 2 14 mhz 3 11 mhz 4 9.6 mhz 5 8.3 mhz 6 7.3 mhz 7 6.6 mhz 8 6 mhz .. 17 3.2 mhz 18 3.0 mhz 19 2.9 mhz 20 2.8 mhz 21 2.7 mhz 22 2.6 mhz 23 2.5 mhz 24 2.4 mhz
september 1993 23 philips semiconductors product speci?cation programmable delay timer with oscillator 74hc/hct5555 package outlines see 74hc/hct/hcu/hcmos logic package outlines . fig.15 external components configuration for a crystal oscillator. handbook, halfpage mlb336 2 rs 1 mr (from logic) r tc r2 2.2 k w c3 r bias 100 k w to 1 m w 22 to 37 pf c2 100 pf fig.16 graphic representation of short time delay accuracy; one stage selected; v cc = 4.5 v. handbook, full pagewidth 600 40 0 0 200 300 mga648 100 500 400 8 16 24 32 4 12 20 28 36 programmed time (ns) deviation (%) max. expected typ. expected min. expected

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